Generally, two types of conventional counters exist, namely, synchronous counters and asynchronous counters. Synchronous counters conventionally are used in a variety of applications, where the frequency of the reference clock is at least as fast as the frequency of the input signal being processed.
Synchronous counters are favored for high-speed applications due to latency and robustness of synchronous sequential circuits. However, synchronous counters tend to be a source of noise at the frequency of the input clock signal. Operation of conventional flip-flops at high frequencies can be a significant contributing factor to such noise. Moreover, capacitive load at the clock input rises quickly with the size of the counter limiting its maximum frequency.
Asynchronous counters on the other hand tend to generate less noise than comparable synchronous counters. Unfortunately, asynchronous counters tend to have large latency in comparison to comparable synchronous counters. Asynchronous counters conventionally divide down frequency of an input signal. Such an input signal is divided down in successive stages, where the output of an immediately preceding stage is the reference clock of the next stage. Thus, propagation delay increases as the number of stages of an asynchronous counter increases.
Accordingly, it would be desirable and useful to provide a high-speed counter with low latency.